Micrel, Inc.
MIC2310
July 2008
16
M9999-070108-A
Charging Load by dI
D
/dt Primary OC Trips CB
after t
POC
and CB Reset by Toggling ENABLE
HIGH-to-LOW
Figure 5 illustrates the behavior of the controller to an
OC event after the primary and secondary OC
detection circuits have been armed (upon the
application of an ENABLE LOW-to-HIGH transition
and after t
POR
). In this example, the load capacitor is
charged at a controlled dI
D
/dt rate. Steady-state
operation is not achieved as the controlled inrush
profile causes the primary OC detector to trigger at
I
POC
and continues charging when the t
POCSENSE
timer
terminates. Note that the controllers PWRGD digital
output does not assert because the output load
voltage profile at no time rises higher than the
controllers V
PGH
threshold voltage and the V
GS
of the
external MOSFET does not rise higher than the
controllers V
GSPGH
threshold voltage.
Once the circuit breaker has latched, the I_FLT digital
output is asserted. When the circuit breaker is tripped
by either the primary OC or secondary OC detectors),
applying a HIGH-to-LOW transition on the ENABLE
pin will reset the circuit breaker. At a delay defined by
t
CBRESET
, the internal circuit breaker is reset and is
indicated when the I_FLT digital output becomes de-
asserted. The earliest a LOW-to-HIGH transition at
ENABLE is permitted to initiate a new start-up
sequence is defined by the t
ENLPW
timing specification.
V
CC
= 12V, nominal
V
VREG(UVLOH)
= +4.25V
V
REG
= 5V, nominal
Figure 5. dI
D
/dt Load Charge Profile w/ Primary OC Circuit Breaker (CB) Trip w/ CB Reset
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